The present invention relates to electronic circuits, and more particularly to phase-locked loops and charge pumps adapted for use therewith.
Phase-locked loops (PLLs) are widely used to generate clock signals. Using feedback, the PLL generates one or more output signals having a phase and frequency that closely tracks a reference signal while maintaining stability and satisfying performance requirements.
Some or all of the components of a modern PLL may be embodied in an integrated circuit. Integrated circuits containing PLLs are used in a broad range of applications. In many of these applications, low power consumption and fast response times are important design considerations.
FIG. 2 shows a charge pump 200 as known in the prior art. In operation, a constant current flows in charge pump 200 as the PLL approaches and achieves lock. As shown, transistor Q5 responds to signal UPB by causing a current to flow into node N1 and transistor Q6 responds to signal DNB by causing a current to flow into node N2. These currents significantly increase charge pump power consumption. There is thus a need in the art for low-power PLLs and related components.